1. Field of the Invention
The invention relates to the fabrication of integrated circuits, more specifically to a process for depositing dielectric layers on a substrate, and to the structures formed by the dielectric layer.
2. Description of the Related Art
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 μm and even 0.18 μm feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries.
To further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and to use insulators having low dielectric constants (dielectric constants of less than 4.0) to also reduce the capacitive coupling between adjacent metal lines. One such low k material is silicon oxycarbide deposited by a chemical vapor deposition process and silicon carbide, both of which may be used as dielectric materials in fabricating damascene features.
One conductive material having a low resistivity is copper and its alloys, which have become the materials of choice for sub-quarter-micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 μΩ-cm for copper compared to 3.1 μΩ-cm for aluminum), a higher current and higher carrying capacity. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
One difficulty in using copper in semiconductor devices is that copper is difficult to etch and achieve a precise pattern. Etching with copper using traditional deposition/etch processes for forming interconnects has been less than satisfactory. Therefore, new methods of manufacturing interconnects having copper containing materials and low k dielectric materials are being developed.
One method for forming vertical and horizontal interconnects is by a damascene or dual damascene method. In the damascene method, one or more dielectric materials, such as the low k dielectric materials, are deposited and pattern etched to form the vertical interconnects, e.g., vias, and horizontal interconnects, e.g., lines. Conductive materials, such as copper containing materials, and other materials, such as barrier layer materials used to prevent diffusion of copper containing materials into the surrounding low k dielectric, are then inlaid into the etched pattern. Any excess copper containing materials and excess barrier layer material external to the etched pattern, such as on the field of the substrate, is then removed.
However, low k dielectric materials are often porous and susceptible to interlayer diffusion of conductive materials, such as copper, which can result in the formation of short-circuits and device failure. A dielectric barrier layer material is often disposed between the copper material and surrounding the low k material to prevent interlayer diffusion. However, traditional dielectric barrier layer materials, such as silicon nitride, often have high dielectric constants of 7 or greater. The combination of such a high k dielectric material with surrounding low k dielectric materials results in dielectric stacks having a higher than desired dielectric constant.
Further when silicon oxycarbide layers or silicon carbide layers are used as the low k material in damascene formation, it has been difficult to produced aligned features with little or no defects. It as been observed that resist materials deposited on the silicon oxycarbide layers or the silicon carbide layers may be contaminated with nitrogen deposited with those layers or nitrogen that diffuses through those layers. For example, reaction of organosilicon compounds with nitrous oxide can contaminate the silicon oxycarbide layer with nitrogen or the nitrogen in nitrogen-doped silicon carbide layers may diffuse through adjacent layers as amine radicals (—NH2) to react with the resist materials.
Resist materials contaminated with nitrogen becomes less sensitive to radiation. The decrease in the sensitivity to radiation is referred to as “resist poisoning”. Any resist material that is not sensitive to radiation is not removed by subsequent resist stripping processes and remains as residue. The remaining residue of resist material is referred to as “footing”. This residue can result in detrimentally affecting subsequent etching processes and result in misaligned and malformed features.
One potential solution, the use of nitrogen free barrier layers have not performed as well as expected to provide suitable replacement for nitrogen containing barrier layers. For example, nitrogen free barrier layers have exhibited a loss of hermeticity, or atmosphere or moisture resistance, in the deposited layers, and allow moisture diffusion through layers during processing at high temperature when moisture may evolve from the deposited materials. Moisture in the deposited layer may detrimentally affect layer deposition and be a source of oxidation of deposited metals, and can even result in device failure.
Therefore, there remains a need for an improved process for depositing dielectric material and resist materials for layering techniques, such as damascene applications, with improved hermeticity.